Recovered visual6502.org wiki - beta release
Welcome to the JSSim javascript simulator which powers the Visual6502 and Visual6800.
Please have a look around this wiki for more information about our reverse engineering of various chips and the things we’ve found out about them.
For a quick selection of examples of 6502 behaviour and layout, have a look at the links in the URL interface section on this page. Sorry, we don’t yet have specific help on 6800 features.
The visual6502 simulator has two entry pages:
and this page starts with the basics and works up. There’s also
For help on reading the layout, interpreting transistor circuits, and more about digital design, please see the Visual Circuit Tutorial over at NESdev.
Contents
In simple mode, you see the chip graphics on the left, the control buttons and chip status at top right, and the memory table below that. There’s a link to the advanced page, and the overall layout is fixed: there are no draggable bars between the sections.
You can pan and zoom the chip graphics using
Click in the graphics area to highlight any shape on the chip: all the connected shapes will be highlighted and the name of the node, if any, will be displayed in the chip status area at top right.
For example, if you click on the square shape at top left of the chip, you’ll see text like
node: 1297 nmi
which tells you that this is the NMI pad - in a real chip, it would be connected to the NMI pin of the package with a gold wire.
The node number is useful only as a unique reference number. If you’re interested in the workings of the simulator you’ll read the source files and see these numbers used to label all the polygons and transistors which are electrically connected and which therefore are at the same voltage - and therefore represent the same logical signal.
Towards the top right you see a set of buttons:
As the simulation runs you can see the yellow box in the memory area (bottom right) indicating which memory location is being read or written. You may also see the contents of memory changing: perhaps the location just to the right of } will count up.
You can’t presently modify the program in the simple page: you need the Advanced page for that.
In advanced mode, there’s an additional area at bottom right which can tabulate the state of the machine, and any signals of interest, phase by phase or instruction by instruction. There’s also a console for programs which perform I/O: it’s possible to interact with a BASIC interpreter for example.
The layout in advanced mode has a couple of draggable boundaries so you can adjust according to what you’re doing.
The chip graphics area has some additional controls, and can be hidden altogether.
Finally, in expert mode you can control the simulator and the graphics using additional URL parameters.
All the graphics controls are immediately below the chip graphics area.
Use the keyboard to zoom in and out (z and x or < and >) and once you’ve zoomed in you can use the mouse to pan around, by clicking and dragging.
If you click on any shape in the chip, the status display (top right) will give you the coordinates and the node number, and the node name if it has one. If you click on a transistor gate, it’ll give you the transistor number. If you shift-click on a node, it’ll highlight all the channel-connected nodes - so you can see which busses are connected by pass gates in the present clock cycle, which gates are writing a bus and which latches are reading it.
The second line of graphics controls allow you to select layer visibility. Chips are designed and fabricated as a series of thin layers in and on the silicon. With these controls you can get a clearer idea of the geometry in each layer. For example, most of the long-distance connections are in metal, with some polysilicon. The logic gates themselves use diffusion and polysilicon only, in general.
The next line of graphics controls allow you to find the geometry corresponding to a node name, or number, or a collection of them. The Clear Highlighting button also clears the logic level indication: all the diffusion becomes yellow, all the polysilicon purple, and the metal translucent.
The ‘Animate during simulation’ checkbox allows you to run the simulation faster, by skipping the logic level highlighting of the chip graphics.
‘Hide Chip Layout’ rearranges the page layout so you can concentrate on the right hand side panels - if you’re looking at the logical behaviour and not the chip layout.
Finally, ‘Link to this location’ provides an URL which you can share, corresponding to the current pan and zoom, so you can discuss whichever interesting layout features you find. For example
At the top of the right hand pane there is a series of buttons:
Any write to location $000f will cause output to the text box at the top of the lower right pane.
Location $D010 acts as a status port and $D011 acts as a data port for reading keyboard input. The status port reads 0 until a character is available.
The lower right pane offers some means of tracing signals of interest:
You can use the ‘Trace these too’ box to list more signals which you’re interested in - you might even use ‘Trace less’ several times to make this the exact list of signals to tabulate.
Some names are handled specially and are not individual signals or busses:
If you need to tabulate a signal which is in negative sense, use a leading minus. For example, ‘-pd’ is the instruction predecode register.
The signal names are mostly taken from Donald Hanson’s block diagram
There’s a variety of parameters which can be passed on the URL, to make it easy to share examples and discoveries as direct links into the simulator. In all cases these are passed like this:
[http://www.visual6502.org/JSSim?name1=value1&name2=value2](http://www.visual6502.org/JSSim/expert.html?panx=239.4&pany=352.7&zoom=10.7&steps=10)
positioning the graphics windowpanx=240&pany=350&zoom=10 select a larger canvas for improved graphical detail (uses more RAM)canvas=2000 suppress the simulation, for faster startup of a purely graphical sessionnosim=true suppressing graphics (same as the Hide Chip Layout button)graphics=false running for a fixed number of clock phasessteps=10 see more groups of interesting signals in the tabulationloglevel=4 add specific signals to the tabulationlogmore=Execute,State,plaOutputs set the fastforward step count (for benchmarking, or interactive programs)headlesssteps=250 load a test program, or patch memory contentsa=0000&d=a2d0de2143 adjust the reset vectorr=0002 set up some input pin transitions (Reset, IRQ, NMI, RDY)reset0=12&reset1=13nmi0=4&nmi1=8irq0=3&irq1=20[1] (RDY not yet in the released version) Note on timings of input transitions Since 2013-06-27, the displayed data for input transitions is shown one phase earlier than previously. This fixes a bug. When re-using a URL with the new version, all the chip behaviour is unchanged, but shifting the display of the input signals has made everything appear correct too. check every signal value against a golden checksum (for checking simulator code changes)steps=99&checksum=0fa98aab label some points of interestAnnotated floorplan of the 6502Some functional blocks of the 6502
The final reference on the URL capabilities is the source code.
See also the ChipSim Simulator page which goes into some detail on the implementation and history of the simulator, and have a look at the source code.
See also the guide to interpreting NMOS layout at the Visual circuit tutorial on the NesDev wiki.
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