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MOS 6502 - VisualChips

MOS 6502

From VisualChips

Contents

• MOS 6502 family
• Our Analysis
• 6502 additional information
• Primary Sources
• Secondary Sources
• Previous Analysis

MOS 6502 family

We have photographs of the metal and lower layers, the polygons captured, the circuit extracted and we have published a javascript simulator. There is an FPGA project to implement the simulation in hardware. We have (as yet) unpublished simulators in python and C.

Our Analysis

Here are some relatively raw materials we’ve collected:

• Comparative photos of the Stack Register in 6502 and 6507
• The Decode ROM (describing the Atari 6507, not exactly the same as the NMOS 6502 used in the visual6502 simulator
• All 256 6502 opcodes named and tabulated

And here is some more interpretive material from our explorations:

• Collected observations of 6502 layout and behaviour.
• The 6502 datapath timing
• The unsupported opcodes
• a detailed explanation of the XAA opcode behaviour
• Implementing a realtime netlist simulation in historical systems using an FPGA

6502 additional information

See also the links page on the main site.

Primary Sources

• Photos of MOS 6502D (also see our website)
• Atari’s 6507 Schematics
• Photos of R6502

Secondary Sources

• Hanson’s Block Diagram
• Balazs’ schematic and documents

Previous Analysis

• Beregnyei Balazs: 6502 Reverse Engineering (translation)
• Mark Ormston: 65xx Processor Data (version 0.2b)
• Ivo van Poorten: 6502 Bugs List
• Neil Parker: The 6502/65C02/65C816 Instruction Set Decoded
• Graham: 6502/6510/8500/8502 Opcode matrix
• Freddy Offenga: 6502 Undocumented Opcodes
• Adam Vardy: Extra Instructions Of The 65XX Series CPU

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